For some time it has been possible to fabricate memory devices such as flash memory that are both reprogrammable and keep their charge when power is removed. Such devices are highly desirable and have many applications from storing a computer system's BIOS to functioning as a memory for devices such as digital cameras. Typically, such memory devices may be reprogrammed hundreds of thousands of times and may be programmed or erased in blocks of, for example, hundreds or thousands of bits.
Such devices may operate by storing a charge in a memory cell. For example, a typical flash memory cell may be programmed to hold a charge in a data storage region of a transistor. Clearly, the memory cell will only be accurate to the extent that the data storage region is able to hold its charge. Unfortunately, some memory cells may suffer charge damage during the fabrication process and hence exhibit poor charge retention during actual operation.
The charge damage may arise as a result of different portions of the memory device being at different potentials during the fabrication process. In this event, charge that moves from the higher to the lower potential region may cause damage to an intervening region, such as the region that is designed to store a charge during actual operation.
Thus, a need has arisen for a way to prevent charge damage to storage areas during fabrication of a memory array.